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[LLVM][AArch64] Add "u" variants of sve.[s,u]hsub intrinsics #170894

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Merged
paulwalker-arm merged 1 commit into from
Dec 12, 2025
Merged

[LLVM][AArch64] Add "u" variants of sve.[s,u]hsub intrinsics #170894

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8 changes: 4 additions & 4 deletions clang/include/clang/Basic/arm_sve.td
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Expand Up @@ -1292,10 +1292,10 @@ defm SVQSUB_S : SInstZPZZ<"svqsub", "csli", "aarch64_sve_sqsub", "aarch64
defm SVQSUB_U : SInstZPZZ<"svqsub", "UcUsUiUl", "aarch64_sve_uqsub", "aarch64_sve_uqsub_u">;
defm SVQSUBR_S : SInstZPZZ<"svqsubr", "csli", "aarch64_sve_sqsubr", "aarch64_sve_sqsub_u", [ReverseMergeAnyBinOp]>;
defm SVQSUBR_U : SInstZPZZ<"svqsubr", "UcUsUiUl", "aarch64_sve_uqsubr", "aarch64_sve_uqsub_u", [ReverseMergeAnyBinOp]>;
defm SVHSUB_S : SInstZPZZ<"svhsub", "csli", "aarch64_sve_shsub", "aarch64_sve_shsub">;
defm SVHSUB_U : SInstZPZZ<"svhsub", "UcUsUiUl", "aarch64_sve_uhsub", "aarch64_sve_uhsub">;
defm SVHSUBR_S : SInstZPZZ<"svhsubr", "csli", "aarch64_sve_shsubr", "aarch64_sve_shsubr">;
defm SVHSUBR_U : SInstZPZZ<"svhsubr", "UcUsUiUl", "aarch64_sve_uhsubr", "aarch64_sve_uhsubr">;
defm SVHSUB_S : SInstZPZZ<"svhsub", "csli", "aarch64_sve_shsub", "aarch64_sve_shsub_u">;
defm SVHSUB_U : SInstZPZZ<"svhsub", "UcUsUiUl", "aarch64_sve_uhsub", "aarch64_sve_uhsub_u">;
defm SVHSUBR_S : SInstZPZZ<"svhsubr", "csli", "aarch64_sve_shsubr", "aarch64_sve_shsub_u", [ReverseMergeAnyBinOp]>;
defm SVHSUBR_U : SInstZPZZ<"svhsubr", "UcUsUiUl", "aarch64_sve_uhsubr", "aarch64_sve_uhsub_u", [ReverseMergeAnyBinOp]>;

defm SVQABS : SInstZPZ<"svqabs", "csil", "aarch64_sve_sqabs">;
defm SVQNEG : SInstZPZ<"svqneg", "csil", "aarch64_sve_sqneg">;
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64 changes: 32 additions & 32 deletions clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_hsub.c
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64 changes: 32 additions & 32 deletions clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_hsubr.c
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2 changes: 2 additions & 0 deletions llvm/include/llvm/IR/IntrinsicsAArch64.td
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Expand Up @@ -2435,6 +2435,7 @@ def int_aarch64_sve_stnt1_scatter_scalar_offset : AdvSIMD_ScatterStore_VS_Intri
def int_aarch64_sve_saba : AdvSIMD_3VectorArg_Intrinsic<[IntrSpeculatable]>;
def int_aarch64_sve_shadd : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>;
def int_aarch64_sve_shsub : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>;
def int_aarch64_sve_shsub_u : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>;
def int_aarch64_sve_shsubr : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>;
def int_aarch64_sve_sli : AdvSIMD_2VectorArgIndexed_Intrinsic<[IntrSpeculatable]>;
def int_aarch64_sve_sqabs : AdvSIMD_Merged1VectorArg_Intrinsic<[IntrSpeculatable]>;
Expand Down Expand Up @@ -2467,6 +2468,7 @@ def int_aarch64_sve_suqadd : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpecul
def int_aarch64_sve_uaba : AdvSIMD_3VectorArg_Intrinsic<[IntrSpeculatable]>;
def int_aarch64_sve_uhadd : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>;
def int_aarch64_sve_uhsub : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>;
def int_aarch64_sve_uhsub_u : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>;
def int_aarch64_sve_uhsubr : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>;
def int_aarch64_sve_uqadd : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>;
def int_aarch64_sve_uqrshl : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>;
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11 changes: 7 additions & 4 deletions llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
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Expand Up @@ -3838,12 +3838,15 @@ let Predicates = [HasSVE2_or_SME] in {
// SVE2 integer halving add/subtract (predicated)
defm SHADD_ZPmZ : sve2_int_arith_pred<0b100000, "shadd", AArch64shadd>;
defm UHADD_ZPmZ : sve2_int_arith_pred<0b100010, "uhadd", AArch64uhadd>;
defm SHSUB_ZPmZ : sve2_int_arith_pred<0b100100, "shsub", int_aarch64_sve_shsub>;
defm UHSUB_ZPmZ : sve2_int_arith_pred<0b100110, "uhsub", int_aarch64_sve_uhsub>;
defm SHSUB_ZPmZ : sve2_int_arith_pred<0b100100, "shsub", int_aarch64_sve_shsub, "SHSUB_ZPZZ", DestructiveBinaryCommWithRev, "SHSUBR_ZPmZ">;
defm UHSUB_ZPmZ : sve2_int_arith_pred<0b100110, "uhsub", int_aarch64_sve_uhsub, "UHSUB_ZPZZ", DestructiveBinaryCommWithRev, "UHSUBR_ZPmZ">;
defm SRHADD_ZPmZ : sve2_int_arith_pred<0b101000, "srhadd", AArch64srhadd>;
defm URHADD_ZPmZ : sve2_int_arith_pred<0b101010, "urhadd", AArch64urhadd>;
defm SHSUBR_ZPmZ : sve2_int_arith_pred<0b101100, "shsubr", int_aarch64_sve_shsubr>;
defm UHSUBR_ZPmZ : sve2_int_arith_pred<0b101110, "uhsubr", int_aarch64_sve_uhsubr>;
defm SHSUBR_ZPmZ : sve2_int_arith_pred<0b101100, "shsubr", int_aarch64_sve_shsubr, "SHSUBR_ZPZZ", DestructiveBinaryCommWithRev, "SHSUB_ZPmZ", /*isReverseInstr*/ 1>;
defm UHSUBR_ZPmZ : sve2_int_arith_pred<0b101110, "uhsubr", int_aarch64_sve_uhsubr, "UHSUBR_ZPZZ", DestructiveBinaryCommWithRev, "UHSUB_ZPmZ", /*isReverseInstr*/ 1>;

defm SHSUB_ZPZZ : sve_int_bin_pred_bhsd<int_aarch64_sve_shsub_u>;
defm UHSUB_ZPZZ : sve_int_bin_pred_bhsd<int_aarch64_sve_uhsub_u>;

// SVE2 integer pairwise add and accumulate long
defm SADALP_ZPmZ : sve2_int_sadd_long_accum_pairwise<0, "sadalp", int_aarch64_sve_sadalp>;
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64SchedA320.td
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Expand Up @@ -674,7 +674,7 @@ def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>],
"^(ADD|SUB|SUBR)_ZI_[BHSD]",
"^ADR_[SU]XTW_ZZZ_D_[0123]",
"^ADR_LSL_ZZZ_[SD]_[0123]",
"^[SU]H(ADD|SUB|SUBR)_ZPmZ_[BHSD]")>;
"^[SU]H(ADD|SUB|SUBR)_(ZPmZ|ZPZZ)_[BHSD]")>;
def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>],
(instregex "^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]",
"^SADDLBT_ZZZ_[HSD]",
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64SchedA510.td
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Expand Up @@ -652,7 +652,7 @@ def : InstRW<[CortexA510Write<3, CortexA510UnitVALU>],
"^(ADD|SUB|SUBR)_ZI_[BHSD]",
"^ADR_[SU]XTW_ZZZ_D_[0123]",
"^ADR_LSL_ZZZ_[SD]_[0123]",
"^[SU]H(ADD|SUB|SUBR)_ZPmZ_[BHSD]")>;
"^[SU]H(ADD|SUB|SUBR)_(ZPmZ|ZPZZ)_[BHSD]")>;
def : InstRW<[CortexA510Write<4, CortexA510UnitVALU>],
(instregex "^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]",
"^SADDLBT_ZZZ_[HSD]",
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
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Expand Up @@ -1662,7 +1662,7 @@ def : InstRW<[N2Write_2c_1V],
"^ADR_LSL_ZZZ_[SD]_[0123]",
"^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]",
"^SADDLBT_ZZZ_[HSD]",
"^[SU]H(ADD|SUB|SUBR)_ZPmZ_[BHSD]",
"^[SU]H(ADD|SUB|SUBR)_(ZPmZ|ZPZZ)_[BHSD]",
"^SSUBL(BT|TB)_ZZZ_[HSD]")>;

// Arithmetic, complex
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td
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Expand Up @@ -1752,7 +1752,7 @@ def : InstRW<[N3Write_2c_1V],
"^ADR_LSL_ZZZ_[SD]_[0123]",
"^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]",
"^SADDLBT_ZZZ_[HSD]",
"^[SU]H(ADD|SUB|SUBR)_ZPmZ_[BHSD]",
"^[SU]H(ADD|SUB|SUBR)_(ZPmZ|ZPZZ)_[BHSD]",
"^SSUBL(BT|TB)_ZZZ_[HSD]")>;

// Arithmetic, complex
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
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Expand Up @@ -2125,7 +2125,7 @@ def : InstRW<[V2Write_2c_1V],
"^ADR_LSL_ZZZ_[SD]_[0123]",
"^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]",
"^SADDLBT_ZZZ_[HSD]",
"^[SU]H(ADD|SUB|SUBR)_ZPmZ_[BHSD]",
"^[SU]H(ADD|SUB|SUBR)_(ZPmZ|ZPZZ)_[BHSD]",
"^SSUBL(BT|TB)_ZZZ_[HSD]")>;

// Arithmetic, complex
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64SchedNeoverseV3.td
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Expand Up @@ -2054,7 +2054,7 @@ def : InstRW<[V3Write_2c_1V],
"^ADR_LSL_ZZZ_[SD]_[0123]",
"^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]",
"^SADDLBT_ZZZ_[HSD]",
"^[SU]H(ADD|SUB|SUBR)_ZPmZ_[BHSD]",
"^[SU]H(ADD|SUB|SUBR)_(ZPmZ|ZPZZ)_[BHSD]",
"^SSUBL(BT|TB)_ZZZ_[HSD]")>;

// Arithmetic, complex
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64SchedNeoverseV3AE.td
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Expand Up @@ -1982,7 +1982,7 @@ def : InstRW<[V3AEWrite_2c_1V],
"^ADR_LSL_ZZZ_[SD]_[0123]",
"^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]",
"^SADDLBT_ZZZ_[HSD]",
"^[SU]H(ADD|SUB|SUBR)_ZPmZ_[BHSD]",
"^[SU]H(ADD|SUB|SUBR)_(ZPmZ|ZPZZ)_[BHSD]",
"^SSUBL(BT|TB)_ZZZ_[HSD]")>;

// Arithmetic, complex
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8 changes: 8 additions & 0 deletions llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
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Expand Up @@ -1457,6 +1457,10 @@ static SVEIntrinsicInfo constructSVEIntrinsicInfo(IntrinsicInst &II) {
case Intrinsic::aarch64_sve_orr:
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_orr_u)
.setMatchingIROpcode(Instruction::Or);
case Intrinsic::aarch64_sve_shsub:
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_shsub_u);
case Intrinsic::aarch64_sve_shsubr:
return SVEIntrinsicInfo::defaultMergingOp();
case Intrinsic::aarch64_sve_sqrshl:
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_sqrshl_u);
case Intrinsic::aarch64_sve_sqshl:
Expand All @@ -1465,6 +1469,10 @@ static SVEIntrinsicInfo constructSVEIntrinsicInfo(IntrinsicInst &II) {
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_sqsub_u);
case Intrinsic::aarch64_sve_srshl:
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_srshl_u);
case Intrinsic::aarch64_sve_uhsub:
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_uhsub_u);
case Intrinsic::aarch64_sve_uhsubr:
return SVEIntrinsicInfo::defaultMergingOp();
case Intrinsic::aarch64_sve_uqrshl:
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_uqrshl_u);
case Intrinsic::aarch64_sve_uqshl:
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