Map L2CFG region to tlb

kernel/init/boot/boot.ref.S

@@ -397,10 +397,10 @@ boot_continuation:
 	TLB_PHYS = PHYS_ADDR
 
 	TLB_INDEX = sub(LAST_TLB, NPAGES)
-#ifdef NULL_ANGEL_TRAP	
-	TLB_INDEX = add(TLB_INDEX, #-1)
+#ifdef NULL_ANGEL_TRAP
+	TLB_INDEX = add(TLB_INDEX, #-2)  // -2 for l2regs and device page: starting index for pinned entries
 #else
-	TLB_INDEX = add(TLB_INDEX, #-2)  // -2 for angel and device page: starting index for pinned entries
+	TLB_INDEX = add(TLB_INDEX, #-3)  // -3 for angel, l2regs, and device page: starting index for pinned entries
 #endif
 	LAST_TLB = add(TLB_INDEX, #-1) // last free entry
 	COUNTER = #0
@@ -434,6 +434,23 @@ boot_continuation:
 	MAKE_TLBLO_DEV(TLB_LO, SS_BASE, TLB_TMP)
 	DO_TLBW
 
+#undef SYSCFG
+#undef SIG_COUNT
+#undef FROM
+#define CFG_IDX r8
+#define CFG_HI r9
+#define L2_CFG_BASE r11
+
+	TLB_INDEX = add(TLB_INDEX, #1)
+	MAKE_TLBHI(TLB_HI, L2CFG_BASE_VA, BOOT_TLB_OFFSET_BITS_1M, BOOT_TLB_SHIFT_1M)
+	CFG_HI = cfgbase
+	CFG_HI = asl(CFG_HI, #(CFG_TABLE_SHIFT - PHYSREAD_HI_SHIFT))
+	CFG_IDX = #CFG_TABLE_L2REGS
+	L2_CFG_BASE = memw_phys(CFG_IDX, CFG_HI)
+	L2_CFG_BASE = asl(L2_CFG_BASE, #CFG_TABLE_SHIFT)
+	MAKE_TLBLO_DEV(TLB_LO, L2_CFG_BASE, TLB_TMP)
+	DO_TLBW
+
 #ifndef NULL_ANGEL_TRAP
 	// entry for angel (0 page)
 	TLB_INDEX = add(TLB_INDEX, #1)

kernel/traps/hwconfig/hwconfig.ref.c

@@ -96,39 +96,33 @@ u32_t H2K_trap_hwconfig(hwconfig_type_t configtype, void *ptr, u32_t val2, u32_t
 }
 
 static u32_t getxreg (u32_t cfg_offset, u32_t offset) {
-	u32_t va;
 	pa_t base;
+	u32_t page_off;
 	u32_t volatile *reg;
-	u32_t ret;
 
 	offset &= -4;
 
 	base = H2K_cfg_table(cfg_offset) << CFG_TABLE_SHIFT;
+	page_off = base & SIZE_1M_MASK;
+	reg = (u32_t volatile *) (L2CFG_BASE_VA + page_off + offset);
 
-	va = H2K_tmpmap_add_and_lock(base, UNCACHED, SIZE_DEFAULT);
-	reg = (u32_t *) (va + offset);
-	ret = *reg;
-	H2K_tmpmap_remove_and_unlock();
-
-	return ret;
+	return *reg;
 }
 
 static u32_t setxreg(u32_t cfg_offset, u32_t offset, u32_t val) {
-	u32_t va;
 	pa_t base;
+	u32_t page_off;
 	u32_t volatile *reg;
 	u32_t ret;
 
 	offset &= -4;
 
 	base = H2K_cfg_table(cfg_offset) << CFG_TABLE_SHIFT;
-
-	va = H2K_tmpmap_add_and_lock(base, UNCACHED, SIZE_DEFAULT);
-	reg = (u32_t *) (va + offset);
+	page_off = base & SIZE_1M_MASK;
+	reg = (u32_t volatile *) (L2CFG_BASE_VA + page_off + offset);
 	ret = *reg;
 	*reg = val;
 	H2K_dccleana((void *)reg);
-	H2K_tmpmap_remove_and_unlock();
 
 	return ret;
 }

kernel/util/max/max.h

@@ -94,6 +94,7 @@
 /* Hardware threads this build supports; never start or account beyond it. */
 #define MAX_HTHREADS_MASK ((1U << MAX_HTHREADS) - 1)
 
+
 /* QDSP6SS_PRIV_BASE is the subsystem base value read from cfg_table, but we
 	 map QDSP6SS_PUB_BASE to Q6_SS_BASE_VA so we can get at the public registers.
 	 FIXME? Is the QDSP6SS_PUB_PRIV_OFFSET the same for all subsystems? */
@@ -103,7 +104,9 @@
 #define Q6_SS_BASE_VA 0xffc00000  // leaves at most 4M for tmpmap at 0xff800000
 #define QDSP6SS_PUB_PRIV_OFFSET 0x80000
 
-#define ANGEL_VA 0xffd00000
+#define L2CFG_BASE_VA 0xffd00000
+
+#define ANGEL_VA 0xffe00000
 #define ANGEL_PG_SIZE SIZE_4K
 
 #if ARCHV == 4

libs/h2/common/h2_common_pmap.h

@@ -24,6 +24,17 @@
 #define PAGE_SIZE_MAX SIZE_1G
 #endif
 
+#define SIZE_4K_MASK   0xfff
+#define SIZE_16K_MASK  0x3fff
+#define SIZE_64K_MASK  0xffff
+#define SIZE_256K_MASK 0x3ffff
+#define SIZE_1M_MASK   0xfffff
+#define SIZE_4M_MASK   0x3fffff
+#define SIZE_16M_MASK  0xffffff
+#define SIZE_64M_MASK  0x3ffffff
+#define SIZE_256M_MASK 0xfffffff
+#define SIZE_1G_MASK   0x3fffffff
+
 #define L1WB_L2UC 0
 #define L1WT_L2UC 1
 #define DEVICE_TYPE_SFC 2