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fix(dts): align XiangShan ISA declarations with RVA23 profiles #53

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ac3ed87
fix(dts): align isa extention with rva23
rezado Aug 26, 2026
42966c7
fix(dts): remove v for all novec and fix 16gb dts
rezado Aug 26, 2026
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16 changes: 8 additions & 8 deletions dts/xiangshan-fpga-noAIA-2hart-mem16g-novec.dts.in
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,7 @@
* workload template while using the FPGA board interrupt/peripheral
* map below.
*/
riscv,isa = "rv64imafdch_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa = "rv64imafdch_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions =
"i", "m", "a", "f", "d", "c", "h",
Expand All @@ -56,10 +56,10 @@
"sspm", "ssstateen", "ssstrict",
"sstvala", "sstvecd", "ssu64xl", "supm",
"sv39", "sv48", "svade", "svbare", "svinval",
"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
"svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs",
"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b",
"zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "ziccrse",
"zicntr", "zicond", "zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm", "zimop",
Expand Down Expand Up @@ -103,7 +103,7 @@
* workload template while using the FPGA board interrupt/peripheral
* map below.
*/
riscv,isa = "rv64imafdch_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa = "rv64imafdch_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions =
"i", "m", "a", "f", "d", "c", "h",
Expand All @@ -116,10 +116,10 @@
"sspm", "ssstateen", "ssstrict",
"sstvala", "sstvecd", "ssu64xl", "supm",
"sv39", "sv48", "svade", "svbare", "svinval",
"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
"svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs",
"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b",
"zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "ziccrse",
"zicntr", "zicond", "zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm", "zimop",
Expand Down
16 changes: 8 additions & 8 deletions dts/xiangshan-fpga-noAIA-2hart-mem8g-novec.dts.in
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,7 @@
* workload template while using the FPGA board interrupt/peripheral
* map below.
*/
riscv,isa = "rv64imafdch_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa = "rv64imafdch_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions =
"i", "m", "a", "f", "d", "c", "h",
Expand All @@ -56,10 +56,10 @@
"sspm", "ssstateen", "ssstrict",
"sstvala", "sstvecd", "ssu64xl", "supm",
"sv39", "sv48", "svade", "svbare", "svinval",
"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
"svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs",
"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b",
"zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "ziccrse",
"zicntr", "zicond", "zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm", "zimop",
Expand Down Expand Up @@ -103,7 +103,7 @@
* workload template while using the FPGA board interrupt/peripheral
* map below.
*/
riscv,isa = "rv64imafdch_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa = "rv64imafdch_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions =
"i", "m", "a", "f", "d", "c", "h",
Expand All @@ -116,10 +116,10 @@
"sspm", "ssstateen", "ssstrict",
"sstvala", "sstvecd", "ssu64xl", "supm",
"sv39", "sv48", "svade", "svbare", "svinval",
"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
"svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs",
"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b",
"zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "ziccrse",
"zicntr", "zicond", "zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm", "zimop",
Expand Down
256 changes: 128 additions & 128 deletions dts/xiangshan-fpga-noAIA-32hart-mem64g.dts.in
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Large diffs are not rendered by default.

8 changes: 4 additions & 4 deletions dts/xiangshan-fpga-noAIA-mem128g-novec.dts.in
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,7 @@
* workload template while using the FPGA board interrupt/peripheral
* map below.
*/
riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa = "rv64imafdch_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions =
"i", "m", "a", "f", "d", "c", "h",
Expand All @@ -56,10 +56,10 @@
"sspm", "ssstateen", "ssstrict", "sstc",
"sstvala", "sstvecd", "ssu64xl", "supm",
"sv39", "sv48", "svade", "svbare", "svinval",
"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
"svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs",
"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b",
"zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "ziccrse",
"zicntr", "zicond", "zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm", "zimop",
Expand Down
22 changes: 19 additions & 3 deletions dts/xiangshan-fpga-noAIA-mem16g-novec.dts.in
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Original file line number Diff line number Diff line change
Expand Up @@ -24,12 +24,28 @@
reg = <0>;
status = "okay";
mmu-type = "riscv,sv48";
riscv,isa = "rv64imafdch_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa = "rv64imafdch_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions =
"i", "m", "a", "f", "d", "c", "h",
"smstateen", "sscofpmf", "sstc", "zicntr", "zihpm",
"svpbmt", "sdtrig", "smcsrind", "sscsrind", "svade";
"sdtrig", "sha", "shcounterenw", "shgatpa",
"shlcofideleg", "shtvala", "shvsatpa", "shvstvala",
"shvstvecd", "smcsrind", "smdbltrp",
"smmpm", "smnpm", "smstateen",
"ss1p13", "ssccptr", "sscofpmf",
"sscounterenw", "sscsrind", "ssdbltrp", "ssnpm",
"sspm", "ssstateen", "ssstrict", "sstc",
"sstvala", "sstvecd", "ssu64xl", "supm",
"sv39", "sv48", "svade", "svbare", "svinval",
"svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs",
"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
"zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "ziccrse",
"zicntr", "zicond", "zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm", "zimop",
"zkn", "zknd", "zkne", "zknh", "zksed",
"zksh", "zkt";

intc_cpu0: interrupt-controller {
#interrupt-cells = <1>;
Expand Down
8 changes: 4 additions & 4 deletions dts/xiangshan-fpga-noAIA-mem24g-novec.dts.in
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Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,7 @@
* workload template while using the FPGA board interrupt/peripheral
* map below.
*/
riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa = "rv64imafdch_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions =
"i", "m", "a", "f", "d", "c", "h",
Expand All @@ -56,10 +56,10 @@
"sspm", "ssstateen", "ssstrict", "sstc",
"sstvala", "sstvecd", "ssu64xl", "supm",
"sv39", "sv48", "svade", "svbare", "svinval",
"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
"svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs",
"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b",
"zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "ziccrse",
"zicntr", "zicond", "zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm", "zimop",
Expand Down
8 changes: 4 additions & 4 deletions dts/xiangshan-fpga-noAIA-mem24g.dts.in
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Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,7 @@
* workload template while using the FPGA board interrupt/peripheral
* map below.
*/
riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions =
"i", "m", "a", "f", "d", "c", "v", "h",
Expand All @@ -56,10 +56,10 @@
"sspm", "ssstateen", "ssstrict", "sstc",
"sstvala", "sstvecd", "ssu64xl", "supm",
"sv39", "sv48", "svade", "svbare", "svinval",
"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
"svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs",
"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b",
"zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "ziccrse",
"zicntr", "zicond", "zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm", "zimop",
Expand Down
8 changes: 4 additions & 4 deletions dts/xiangshan-fpga-noAIA-mem64g-novec.dts.in
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Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,7 @@
* workload template while using the FPGA board interrupt/peripheral
* map below.
*/
riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa = "rv64imafdch_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions =
"i", "m", "a", "f", "d", "c", "h",
Expand All @@ -56,10 +56,10 @@
"sspm", "ssstateen", "ssstrict", "sstc",
"sstvala", "sstvecd", "ssu64xl", "supm",
"sv39", "sv48", "svade", "svbare", "svinval",
"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
"svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs",
"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b",
"zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "ziccrse",
"zicntr", "zicond", "zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm", "zimop",
Expand Down
8 changes: 4 additions & 4 deletions dts/xiangshan-fpga-noAIA-mem64g.dts.in
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Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,7 @@
* workload template while using the FPGA board interrupt/peripheral
* map below.
*/
riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions =
"i", "m", "a", "f", "d", "c", "v", "h",
Expand All @@ -56,10 +56,10 @@
"sspm", "ssstateen", "ssstrict", "sstc",
"sstvala", "sstvecd", "ssu64xl", "supm",
"sv39", "sv48", "svade", "svbare", "svinval",
"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
"svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs",
"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b",
"zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "ziccrse",
"zicntr", "zicond", "zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm", "zimop",
Expand Down
8 changes: 4 additions & 4 deletions dts/xiangshan-fpga-noAIA-mem8g-novec.dts.in
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Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,7 @@
* workload template while using the FPGA board interrupt/peripheral
* map below.
*/
riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa = "rv64imafdch_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions =
"i", "m", "a", "f", "d", "c", "h",
Expand All @@ -56,10 +56,10 @@
"sspm", "ssstateen", "ssstrict", "sstc",
"sstvala", "sstvecd", "ssu64xl", "supm",
"sv39", "sv48", "svade", "svbare", "svinval",
"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
"svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs",
"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b",
"zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "ziccrse",
"zicntr", "zicond", "zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm", "zimop",
Expand Down
8 changes: 4 additions & 4 deletions dts/xiangshan-fpga-noAIA-mem8g.dts.in
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Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,7 @@
* workload template while using the FPGA board interrupt/peripheral
* map below.
*/
riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions =
"i", "m", "a", "f", "d", "c", "v", "h",
Expand All @@ -56,10 +56,10 @@
"sspm", "ssstateen", "ssstrict", "sstc",
"sstvala", "sstvecd", "ssu64xl", "supm",
"sv39", "sv48", "svade", "svbare", "svinval",
"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
"svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs",
"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b",
"zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "ziccrse",
"zicntr", "zicond", "zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm", "zimop",
Expand Down
8 changes: 4 additions & 4 deletions dts/xiangshan-fpga-noAIA-novec.dts.in
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Expand Up @@ -43,7 +43,7 @@
* workload template while using the FPGA board interrupt/peripheral
* map below.
*/
riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa = "rv64imafdch_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions =
"i", "m", "a", "f", "d", "c", "h",
Expand All @@ -56,10 +56,10 @@
"sspm", "ssstateen", "ssstrict", "sstc",
"sstvala", "sstvecd", "ssu64xl", "supm",
"sv39", "sv48", "svade", "svbare", "svinval",
"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
"svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs",
"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b",
"zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "ziccrse",
"zicntr", "zicond", "zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm", "zimop",
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8 changes: 4 additions & 4 deletions dts/xiangshan-fpga-noAIA.dts.in
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Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,7 @@
* workload template while using the FPGA board interrupt/peripheral
* map below.
*/
riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions =
"i", "m", "a", "f", "d", "c", "v", "h",
Expand All @@ -56,10 +56,10 @@
"sspm", "ssstateen", "ssstrict", "sstc",
"sstvala", "sstvecd", "ssu64xl", "supm",
"sv39", "sv48", "svade", "svbare", "svinval",
"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
"svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs",
"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b",
"zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin",
"zic64b", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "ziccrse",
"zicntr", "zicond", "zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm", "zimop",
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9 changes: 5 additions & 4 deletions scripts/generate-xiangshan-multihart-dts.py
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Expand Up @@ -5,7 +5,8 @@


MULTIHART_RISCV_ISA = (
"rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_"
"rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_"
"zicntr_zihpm_svpbmt_"
"sdtrig_smcsrind_sscsrind_svade"
)
MULTIHART_CPU_ISA_PROPERTIES = f"""\
Expand All @@ -22,10 +23,10 @@
\t\t\t\t"sspm", "ssstateen", "ssstrict",
\t\t\t\t"sstvala", "sstvecd", "ssu64xl", "supm",
\t\t\t\t"sv39", "sv48", "svade", "svbare", "svinval",
\t\t\t\t"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
\t\t\t\t"svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs",
\t\t\t\t"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
\t\t\t\t"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
\t\t\t\t"zic64b",
\t\t\t\t"zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin",
\t\t\t\t"zic64b", "zicbom", "zicbop", "zicboz",
\t\t\t\t"ziccamoa", "ziccif", "zicclsm", "ziccrse",
\t\t\t\t"zicntr", "zicond", "zicsr", "zifencei",
\t\t\t\t"zihintntl", "zihintpause", "zihpm", "zimop",
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